DMAC - DMAC

 

 

module dmac (
 clk,
 reset_n,
 M_req,
 M_address,
 M_wr,
 M_dout,
 M_grant,
 M_din,
 S_sel,
 S_address,
 S_wr,
 S_din,
 S_dout,
 interrupt,
 fifo_control
);
 input clk;
 input reset_n;
 
 //Master ports
 output    M_req;
 output [7:0] M_address;
 output    M_wr;
 output [7:0] M_dout;
 input    M_grant;
 input  [7:0] M_din;
 
 //Slave ports
 input    S_sel;
 input  [7:0] S_address;
 input    S_wr;
 input  [7:0] S_din;
 output [7:0] S_dout;
 
 //Interrupt signal
 output interrupt;
 //FIFO control signal
 output[5:0] fifo_control;
 
 wire dmac_opstart;
 wire dmac_opdone;
 wire dmac_opdone_clear; 
 wire [2:0] dmac_state;
 
 wire fifo_wren;
 wire [7:0] fifo_din0_srcaddr, fifo_din1_destaddr, fifo_din2_datasize;
 wire [3:0] fifo_data_count;
 
 wire [5:0] fifo_control;
 wire fifo_rden;
 wire [7:0] fifo_dout0_srcaddr, fifo_dout1_destaddr, fifo_dout2_datasize; 
 wire fifo_full, fifo_empty, fifo_wr_ack, fifo_wr_err, fifo_rd_ack, fifo_rd_err;
 
 assign fifo_control = {fifo_full, fifo_empty, fifo_wr_ack, fifo_wr_err, fifo_rd_ack, fifo_rd_err};
 
 dmac_slave U0_dmac_slave(
  .clk(clk),
  .reset_n(reset_n),
  //Slave interface
  .S_sel(S_sel),
  .S_address(S_address),
  .S_wr(S_wr),
  .S_din(S_din),
  .S_dout(S_dout),
  //Interrupt signal
  .interrupt(interrupt),
  //Inner interface
  .dmac_opstart(dmac_opstart), 
  .dmac_opdone(dmac_opdone),
  .dmac_opdone_clear(dmac_opdone_clear),  
  .dmac_state(dmac_state),
  .fifo_wren(fifo_wren),
  .fifo_din0_srcaddr(fifo_din0_srcaddr),
  .fifo_din1_destaddr(fifo_din1_destaddr),
  .fifo_din2_datasize(fifo_din2_datasize),
  .fifo_data_count(fifo_data_count) 
 );
 
 fifo_for_DMAC U1_fifo(
  .clk(clk),
  .reset_n(reset_n),
  .wr_en(fifo_wren),
  .rd_en(fifo_rden),
  .din0(fifo_din0_srcaddr),
  .din1(fifo_din1_destaddr),
  .din2(fifo_din2_datasize),
  .dout0(fifo_dout0_srcaddr),
  .dout1(fifo_dout1_destaddr),
  .dout2(fifo_dout2_datasize),
  .data_count(fifo_data_count),
  .full(fifo_full),
  .empty(fifo_empty),
  .wr_ack(fifo_wr_ack),
  .wr_err(fifo_wr_err),
  .rd_ack(fifo_rd_ack),
  .rd_err(fifo_rd_err)
 );
 
 dmac_master U2_dmac_master(
  .clk(clk),
  .reset_n(reset_n),
  //Master interface
  .M_req(M_req),
  .M_address(M_address),
  .M_wr(M_wr),
  .M_dout(M_dout),
  .M_grant(M_grant),
  .M_din(M_din),  
  //Inner interface
  .dmac_opstart(dmac_opstart),
  .dmac_opdone(dmac_opdone),
  .dmac_opdone_clear(dmac_opdone_clear),  
  .dmac_state(dmac_state),  
  .fifo_rden(fifo_rden),
  .fifo_dout0_srcaddr(fifo_dout0_srcaddr),
  .fifo_dout1_destaddr(fifo_dout1_destaddr),
  .fifo_dout2_datasize(fifo_dout2_datasize),
  .fifo_data_count(fifo_data_count)
 );
 
endmodule