Shifter

* Logical shift Left(LSL)

Register를 Shamt만큼 Shift Left시키고 빈 공간을 0으로 채운다

 

module LSL8(d_in,shamt,d_out);

input [7:0] d_in;
input [1:0] shamt; 
output [7:0] d_out;

mx4 U0_mx4(.y(d_out[7]),.d0(d_in[7]),.d1(d_in[6]),.d2(d_in[5]),.d3(d_in[4]),.s(shamt));
mx4 U1_mx4(.y(d_out[6]),.d0(d_in[6]),.d1(d_in[5]),.d2(d_in[4]),.d3(d_in[3]),.s(shamt));
mx4 U2_mx4(.y(d_out[5]),.d0(d_in[5]),.d1(d_in[4]),.d2(d_in[3]),.d3(d_in[2]),.s(shamt));
mx4 U3_mx4(.y(d_out[4]),.d0(d_in[4]),.d1(d_in[3]),.d2(d_in[2]),.d3(d_in[1]),.s(shamt));
mx4 U4_mx4(.y(d_out[3]),.d0(d_in[3]),.d1(d_in[2]),.d2(d_in[1]),.d3(d_in[0]),.s(shamt));
mx4 U5_mx4(.y(d_out[2]),.d0(d_in[2]),.d1(d_in[1]),.d2(d_in[0]),.d3(0),.s(shamt));
mx4 U6_mx4(.y(d_out[1]),.d0(d_in[1]),.d1(d_in[0]),.d2(0),.d3(0),.s(shamt));
mx4 U7_mx4(.y(d_out[0]),.d0(d_in[0]),.d1(0),.d2(0),.d3(0),.s(shamt));

endmodule

 

 

 

* Logical shift Right(LSR)

Register를 Shamt만큼 Shift Right시키고 빈 공간을 0으로 채운다

 

module LSR8(d_in,shamt,d_out);

input [7:0] d_in;
input [1:0] shamt;
output [7:0] d_out;

mx4 U0_mx4(.y(d_out[7]),.d0(d_in[7]),.d1(0),.d2(0),.d3(0),.s(shamt));
mx4 U1_mx4(.y(d_out[6]),.d0(d_in[6]),.d1(d_in[7]),.d2(0),.d3(0),.s(shamt));
mx4 U2_mx4(.y(d_out[5]),.d0(d_in[5]),.d1(d_in[6]),.d2(d_in[7]),.d3(0),.s(shamt));
mx4 U3_mx4(.y(d_out[4]),.d0(d_in[4]),.d1(d_in[5]),.d2(d_in[6]),.d3(d_in[7]),.s(shamt));
mx4 U4_mx4(.y(d_out[3]),.d0(d_in[3]),.d1(d_in[4]),.d2(d_in[5]),.d3(d_in[6]),.s(shamt));
mx4 U5_mx4(.y(d_out[2]),.d0(d_in[2]),.d1(d_in[3]),.d2(d_in[4]),.d3(d_in[5]),.s(shamt));
mx4 U6_mx4(.y(d_out[1]),.d0(d_in[1]),.d1(d_in[2]),.d2(d_in[3]),.d3(d_in[4]),.s(shamt));
mx4 U7_mx4(.y(d_out[0]),.d0(d_in[0]),.d1(d_in[1]),.d2(d_in[2]),.d3(d_in[3]),.s(shamt));

endmodule 

 

 

* Arithmatic shift Right(ASR)

Register를 Shamt만큼 Shift Right시키고 빈 공간을 MSB으로 채운다

 

module ASR8(d_in,shamt,d_out);

input [7:0] d_in;
input [1:0] shamt;
output [7:0] d_out;

mx4 U0_mx4(.y(d_out[7]),.d0(d_in[7]),.d1(d_in[7]),.d2(d_in[7]),.d3(d_in[7]),.s(shamt));
mx4 U1_mx4(.y(d_out[6]),.d0(d_in[6]),.d1(d_in[7]),.d2(d_in[7]),.d3(d_in[7]),.s(shamt));
mx4 U2_mx4(.y(d_out[5]),.d0(d_in[5]),.d1(d_in[6]),.d2(d_in[7]),.d3(d_in[7]),.s(shamt));
mx4 U3_mx4(.y(d_out[4]),.d0(d_in[4]),.d1(d_in[5]),.d2(d_in[6]),.d3(d_in[7]),.s(shamt));
mx4 U4_mx4(.y(d_out[3]),.d0(d_in[3]),.d1(d_in[4]),.d2(d_in[5]),.d3(d_in[6]),.s(shamt));
mx4 U5_mx4(.y(d_out[2]),.d0(d_in[2]),.d1(d_in[3]),.d2(d_in[4]),.d3(d_in[5]),.s(shamt));
mx4 U6_mx4(.y(d_out[1]),.d0(d_in[1]),.d1(d_in[2]),.d2(d_in[3]),.d3(d_in[4]),.s(shamt));
mx4 U7_mx4(.y(d_out[0]),.d0(d_in[0]),.d1(d_in[1]),.d2(d_in[2]),.d3(d_in[3]),.s(shamt));

endmodule

 

 

* Coding Control Logic

 

module cc_logic(op,shamt,d_in,d_out,do_next);

input [2:0] op; 
input [1:0] shamt;
input [7:0] d_in;
input [7:0] d_out;
output [7:0] do_next;

reg [7:0] do_next;

wire [7:0] d_lsl;
wire [7:0] d_lsr;
wire [7:0] d_asr;

parameter NOP = 3'b000;
parameter LOAD = 3'b001;
parameter LSL = 3'b010;
parameter LSR = 3'b011;
parameter ASR = 3'b100;

always@(op,shamt,d_in,d_out,d_lsl,d_lsr,d_asr)
begin
 case(op)
 NOP: begin
  do_next = d_out; 
  end
 LOAD: begin
  do_next = d_in; 
  end
 LSL:begin
  do_next = d_lsl; 
  end
 LSR:begin
  do_next = d_lsr; 
  end
 ASR:begin
  do_next = d_asr; 

  end
 endcase
end

LSL8 U0_lsl8(.d_in(d_out),.shamt(shamt),.d_out(d_lsl));
LSR8 U1_lsr8(.d_in(d_out),.shamt(shamt),.d_out(d_lsr));

ASR8 U2_asr8(.d_in(d_out),.shamt(shamt),.d_out(d_asr));

endmodule