기본 Gate

* And

module _and2(a,b,y); // 2 input and
input a,b;
output y;
assign y=a&b;  // y = a and b
endmodule

 

* Or

module _or2(a,b,y);  // 2 input or
input a,b;
output y;
assign y=a|b;  // y = a or b
endmodule

 

* Not

module _inv(a,y); // inveter
input a;
output y;
assign y=~a;  // y = not a
endmodule

 

 

* Nand

moodule _nand2(a,b,y);  // 2input nand
input a,b;
output y;
assign y=~(a&b);  // y = not a And b
endmodule

 

* Nor

module _or2(a,b,y);  // 2 input or
input a,b;
output y;
assign y=~(a|b);  // y = a or b
endmodule

 

*  Xor

module _xor2(a,b,y); 
input a,b;
output y;

wire sa,sb;
wire w0,w1;

_inv U0_inv(.a(a),.y(sa)); 

_inv U1_inv(.a(b),.y(sb)); 
_and2 U2_and2(.a(sa),.b(b),.y(w0));

_and2 U3_and2(.a(a),.b(sb),.y(w1));
_or2 U4_or2(.a(w0),.b(w1),.y(y)); 

endmodule

 

---

 

module _xor2(a,b,y);

input a,b;

output y;

 

assign y = a ^ b;

endmodule