DMAC - DMAC
module dmac ( clk, reset_n, M_req, M_address, M_wr, M_dout, M_grant, M_din, S_sel, S_address, S_wr, S_din, S_dout, interrupt, fifo_control ); input clk; input reset_n; //Master ports output M_req; output [7:0] M_address; output M_wr; output [7:0] M_dout; input M_grant; input [7:0] M_din; //Slave ports input S_sel; input [7:0] S_address; input S_wr; input [7:0] S_din; output [7:0] S_dout; //Inter..
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DMAC - FIFO for DMAC
#FIFO for DMAC - 기존 FIFO에서 data in port와 data out port를 3개 늘려서 구현 - 내부에 3개의 Register File을 Instance module fifo_for_DMAC( clk, reset_n, wr_en, rd_en, din0, din1, din2, dout0, dout1, dout2, data_count, full, empty, wr_ack, wr_err, rd_ack, rd_err ); input clk, reset_n, wr_en, rd_en; input [7:0] din0, din1, din2; output reg [7:0] dout0, dout1, dout2; output [3:0] data_count; output reg full, empty,..
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DMAC - MASTER
#Master - Master interface를 통해 data를 read/write하기 위한 DMAC 내부 component #State Diagram module dmac_master( clk, reset_n, //Master interface M_req, M_address, M_wr, M_dout, M_grant, M_din, //Inner interface dmac_opstart, dmac_opdone, dmac_opdone_clear, dmac_state, fifo_rden, fifo_dout0_srcaddr, fifo_dout1_destaddr, fifo_dout2_datasize, fifo_data_count ); input clk; input reset_n; //Master interfac..
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